by Yilou Wang | Jul 4, 2025 | Uncategorized
In our last blog, we described how we implemented constrained randomization support for various array types in Verilator. Building on that, we’ve now extended this functionality to support structs as well, including more complex scenarios where structs and arrays are...
by Yilou Wang | Feb 7, 2025 | Uncategorized
The DI-OSVISE project (De:sign Initiative – Open Source Verification of RISC-V Instruction Set Extensions), funded by the BMBF, aims to advance open-source tools for sustainable and reliable microelectronics in Germany and Europe. One of the goals of our...
by Basit Sajjad | Dec 10, 2024 | Uncategorized
In this post, we will explore the challenges of building an SoC using Amaranth HDL to create the top-level design and integrate pre-existing SystemVerilog modules. Amaranth HDL is a modern, Python-based hardware description language designed to simplify hardware...
by Massimiliano Giacometti | Nov 27, 2024 | Uncategorized
I came across this very interesting paper from Andreas Lööw, A Proof-Producing Translator for Verilog Development in HOL, and that piqued my curiosity. Speaking as a digital design architect, it would indeed be very interesting to be able to generate RTL code upon a...
by Yilou Wang | Nov 7, 2024 | Uncategorized
Randomness Unleashed: Basic Randomization in Verilator In a previous blog post, If-Else Constraint Support, we dove into the importance of Constrained Random Testing (CRT) for verification, and we emphasized just how crucial randomization is to SystemVerilog....
by Yilou Wang | Oct 8, 2024 | Uncategorized
A primary objective of OSVISE is to foster innovation, and PlanV as a part of this initiative, is working to bridge the gap between open-source verification and industry benchmarks, by enhancing UVM support in Verilator. To accelerate our contribution to Verilator,...
