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CVA6’s Instruction and WriteBack Data cache

A RISC-V MCU to for ROS2

roscore-v – this is the name of the latest project we’ve started together with Acceleration Robotics, a Spanish robotics semiconductor startup that designs robot compute architectures to make robots faster. The roscore-v project aims to optimize the ROS processing flow by creating a native ROS 2 hardware implementation in an RISC-V MCU, a dedicated hardwareContinue reading “A RISC-V MCU to for ROS2”

3…2…1 Let’s start with Culsans!

Culsans – the Etruscan version of Janus, the two-faced and also four-faced god, god of the first and last of the year, of the beginning and the end, of the cardinal points and thus of order in general. For us, Culsans is a tightly-coupled cache coherency unit for a multi-core processor based on CVA6.Like theContinue reading “3…2…1 Let’s start with Culsans!”

Adding IRQ support to CVA6 in LiteX

Porting OpenHW’s CVA6 to Litex

I’ve just seen the LiteX‘s console appearing on my terminal after booting my Digilent Nexys A7 board with a LiteX bitfile containinig OpenHW’s CVA6 core. __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2022 Enjoy-Digital (c) Copyright 2007-2015 M-LabsContinue reading “Porting OpenHW’s CVA6 to Litex”