PlanV has already contributed to a collection of projects. These include:
4 Core Snoop Cache Coherency Scheme: Cache coherency isn’t a task for the timid. It frightens some very well seasoned teams. It involves modifying how the core transacts with memory by substituting cache protocol transactions for cache related transactions, and involves creating a new interconnect that manages the transactions between the master and slave components of the system. PlanV has already designed this scheme and has implemented the scheme. It is undergoing verification and it is expected that the solution will be used in platform that will be tapeout by the end of the year.
FPGA based Laser Control System: PlanV supported this client support in the verification of its FPGA-based laser controller deployed in medical field. In particular this support involved the creation of unit tests, employment of tools to provide coverage reports, the review of code against guidelines, a documentation review and the creation doxygen document target in the work flow.
Fault Injector IP Block: PlanV designed, implemented and verified a FPGA based fault injector block to a RISC-V core, the purpose of which was to test the RISC-V core’s behaviour. Injected errors normally result in skipping one or more instructions. The brief for the design of this block was for it to be non invasive, configurable, interact with debug module, sync with the core execution and inform the SW the status of the system, and finally to communicate with a host PC via UART.
Digital Subsystem Fast Pixel Sensor IP Block: This PlanV project has two components. One component involved design and implementation of a verification test bench for the digital subsystem of a sensor. The second component involved consultancy on the client’s cadence based work flow.
RISC-V based ROS node: Research has taken place on the integration of ROS (Robotics Operating System) on a RISC-V core, however it is mostly confined to academia. The strength of RISC-V relies in the possibility to have custom instructions and probably to have exotic combination of instruction extensions. PlanV is working with its research partner to develop a demonstration of such a concept. PlanV has designed a SoC with a CORE-V-MCU RISC-V core and an ethernet block IP. Additionally it has integrated the LWIP protocol stack into the ROS.
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