by massimilianogiacometti | Nov 8, 2022 | Uncategorized
Our work on Culsans (see previous blog entry) forced us to become very familiar with the architecture of the caches in CVA6. We did an in-depth analysis of the RTL code and we decided to share these information, given there is not much documentation available on this...
by massimilianogiacometti | Sep 23, 2022 | Uncategorized
roscore-v – this is the name of the latest project we’ve started together with Acceleration Robotics, a Spanish robotics semiconductor startup that designs robot compute architectures to make robots faster. The roscore-v project aims to optimize the ROS...
by massimilianogiacometti | Sep 5, 2022 | Uncategorized
Culsans – the Etruscan version of Janus, the two-faced and also four-faced god, god of the first and last of the year, of the beginning and the end, of the cardinal points and thus of order in general. For us, Culsans is a tightly-coupled cache coherency unit...
by massimilianogiacometti | Jul 12, 2022 | Uncategorized
In the previous blog post we left the CVA6 porting in LiteX basically without interrupt support. Since this is an unacceptable solution, I’ve decided to tackle this problem as second step. What I had to do: remove the definition of the UART_POLLING macro (in...
by massimilianogiacometti | May 25, 2022 | Uncategorized
I’ve just seen the LiteX’s console appearing on my terminal after booting my Digilent Nexys A7 board with a LiteX bitfile containinig OpenHW’s CVA6 core. __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your...
