by Yilou Wang | Nov 7, 2024 | Uncategorized
Randomness Unleashed: Basic Randomization in Verilator In a previous blog post, If-Else Constraint Support, we dove into the importance of Constrained Random Testing (CRT) for verification, and we emphasized just how crucial randomization is to SystemVerilog....
by Yilou Wang | Oct 8, 2024 | Uncategorized
A primary objective of OSVISE is to foster innovation, and PlanV as a part of this initiative, is working to bridge the gap between open-source verification and industry benchmarks, by enhancing UVM support in Verilator. To accelerate our contribution to Verilator,...
by Yilou Wang | Aug 2, 2024 | Uncategorized
PlanV: Enabling UVM Support in Verilator for RISC-V Verification PlanV is a two-year-old startup in the RISC-V domain based in Munich. This blog discusses the progress made under the OSVISE project, which aims to enable UVM support in Verilator to assist in getting...
