by Yilou Wang | Jun 1, 2026 | Uncategorized
“Give me six hours to chop down a tree and I will spend the first four sharpening the axe.” — Abraham Lincoln The Challenge of Scale in Compiler Fixing In our previous post, we introduced the Verilator Gap Checker—an automated framework that hunts for...
by Yilou Wang | Feb 24, 2026 | Uncategorized
The Problem Verilator is the fastest open-source SystemVerilog simulator — 10–100× faster than commercial tools in many scenarios. But it has a well-known gap: incomplete support for the IEEE 1800-2017 SystemVerilog standard. Your UVM testbench runs fine on QuestaSim,...
by Yilou Wang | Jul 4, 2025 | Uncategorized
In our last blog, we described how we implemented constrained randomization support for various array types in Verilator. Building on that, we’ve now extended this functionality to support structs as well, including more complex scenarios where structs and arrays are...
by Yilou Wang | Feb 7, 2025 | Uncategorized
The DI-OSVISE project (De:sign Initiative – Open Source Verification of RISC-V Instruction Set Extensions), funded by the BMBF, aims to advance open-source tools for sustainable and reliable microelectronics in Germany and Europe. One of the goals of our...
by Yilou Wang | Nov 7, 2024 | Uncategorized
Randomness Unleashed: Basic Randomization in Verilator In a previous blog post, If-Else Constraint Support, we dove into the importance of Constrained Random Testing (CRT) for verification, and we emphasized just how crucial randomization is to SystemVerilog....
