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Delving into ITP and HOL4 for digital design and verification

by Massimiliano Giacometti | Nov 27, 2024 | Uncategorized

I came across this very interesting paper from Andreas Lööw, A Proof-Producing Translator for Verilog Development in HOL, and that piqued my curiosity. Speaking as a digital design architect, it would indeed be very interesting to be able to generate RTL code upon a...

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